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| 型號： | LT1970IFE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 500MA ADJ 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1.6 V/µs |
| 增益帶寬積： | 3.6MHz |
| 電流 - 輸入偏壓： | 160nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 800mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1320 (CN2011-ZH PDF) |
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LT1970
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1970fc
PIN FUNCTIONS
VCSNK (Pin 12): Sink Current Limit Control Voltage In-
put. The current sink limit amplier will activate when
the sense voltage between SENSE+ and SENSE– equals
–1.0 VVCSNK/10. VCSNK may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSNK
and VSENSE is linear except for very small input voltages
at VCSNK < 60mV. VSENSE limits at a minimum set point of
4mV typical to insure that the sink and source limit ampli-
ers do not try to operate simultaneously. To force zero
output current, the ENABLE pin can be taken low.
VCSRC (Pin 13): Source Current Limit Control Voltage
Input. The current source limit amplier will activate when
the sense voltage between SENSE+ and SENSE– equals
VVCSRC/10. VCSRC may be set between VCOMMON and
VCOMMON + 6V. The transfer function between VCSRC
and VSENSE is linear except for very small input voltages
at VCSRC < 60mV. VSENSE limits at a minimum set point
of 4mV typical to insure that the sink and source limit
ampliers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
COMMON (Pin 14): Control and ENABLE inputs and ag
outputs are referenced to the COMMON pin. COMMON may
be at any potential between VEE and VCC – 3V. In typical
applications, COMMON is connected to ground.
ENABLE (Pin 15): ENABLE Digital Input Control. When
taken low this TTL-level digital input turns off the ampli-
er output and drops supply current to less than 1mA.
Use the ENABLE pin to force zero output current. Setting
VCSNK = VCSRC = 0V allows IOUT = ±4mV/RSENSE to ow
in or out of VOUT.
ISRC (Pin 16): Sourcing Current Limit Digital Output Flag.
ISRC is an open collector digital output. ISRC pulls low
whenever the sourcing current limit amplier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit ag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISRC may be left open if
this function is not monitored.
ISNK (Pin 17): Sinking Current Limit Digital Output Flag.
ISNK is an open collector digital output. ISNK pulls low
whenever the sinking current limit amplier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit ag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISNK may be left open if
this function is not monitored.
TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD
is an open collector digital output. TSD pulls low whenever
the internal thermal shutdown circuit activates, typically at
a die temperature of 160°C. This pin can sink up to 10mA
of output current. The TSD ag is off when the die tem-
perature is within normal operating temperatures. ISRC,
ISNK and TSD may be wired “OR” together if desired. ISNK
may be left open if this function is not monitored. Thermal
shutdown activation should prompt the user to evaluate
electrical loading or thermal environmental conditions.
V+ (Pin 19):
Output Stage Positive Supply. V+ may equal
VCC or may be smaller in magnitude. Only output stage
current ows through V+, all other current ows into VCC.
V+ may be used to drive the base/gate of an external power
device to boost the amplier’s output current to levels above
the rated 500mA of the on-chip output devices. Unless
used to drive boost transistors, V+ should be decoupled
to ground with a low ESR capacitor.
Package Base: The exposed backside of the package is
electrically connected to the VEE pins on the IC die. The
package base should be soldered to a heat spreading pad
on the PC board that is electrically connected to VEE.
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