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| 型號： | LT1970IFE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 500MA ADJ 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1.6 V/µs |
| 增益帶寬積： | 3.6MHz |
| 電流 - 輸入偏壓： | 160nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 800mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1320 (CN2011-ZH PDF) |
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LT1970
12
1970fc
APPLICATIONS INFORMATION
ENABLE Control
The ENABLE input pin puts the LT1970 into a low sup-
ply current, high impedance output state. The ENABLE
pin responds to TTL threshold levels with respect to the
COMMON pin. Pulling the ENABLE pin low is the best
way to force zero current at the output. Setting VCSNK =
VCSRC = 0V allows the output current to remain as high
as ± 4mV/RSENSE.
In applications such as circuit testers (ATE), it may be
preferable to apply a predetermined test voltage with a
preset current limit to a test node simultaneously. The
ENABLE pin can be used to provide this gating action as
shown in Figure 2. While the LT1970 is disabled, the load
is essentially oating and the input voltage and current
limit control voltages can be set to produce the load test
levels. Enabling the LT1970 then drives the load. The
LT1970 enables and disables in just a few microseconds.
The actual enable and disable times at the load are a
function of the load reactance.
Operating Status Flags
The LT1970 has three digital output indicators; TSD, ISRC
and ISNK. These outputs are open collector drivers referred
to the COMMON pin. The outputs have 36V capabilities
and can sink in excess of 10mA. ISRC and ISNK indicate
activation of the associated current limit amplier. The TSD
output indicates excessive die temperature has caused the
circuit to enter thermal shutdown. The three digital outputs
may be wire “OR’d” together, monitored individually or left
open. These outputs do not affect circuit operation, but
provide an indication of the present operational status of
the chip.
For slow varying output signals, the assertion of a low level
at the current limit output ags occurs when the current
limit threshold is reached. For fast moving signals where
the LT1970 output is moving at the slew limit, typically
1.6V/μs, the ag assertion can be somewhat premature
at typically 75% of the actual current limit value.
The operating status ags are designed to drive LEDs to
provide a visual indication of current limit and thermal
conditions. As such, the transition edges to and from
the active low state are not particularly sharp and may
exhibit some uncertainty. Adding some positive feedback
to the current limit control inputs helps to sharpen these
transitions.
With the values shown in Figure 3, the current limit thresh-
old is reduced by approximately 0.5% when either current
limit status ag goes low. With sharp logic transitions, the
status outputs can be used in a system control loop to
Figure 2. Using the ENABLE pin
VCSRC
COMMON
VEE
VCSNK
V–
FILTER
V+
12V
EN
VCC
ISNK
ISRC
SENSE–
SENSE+
TSD
OUT
+IN
5V
0V
5V
ENABLE
DISABLE
VIN
LT1970
–12V
–IN
RS
1Ω
RL
10Ω
1970 F02
RG
10k
RF
10k
EN
10V/DIV
0V
VOUT
1V/DIV
5μs/DIV
0V
VIN = 0.5V
VIN = –0.5V
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