參數(shù)資料
型號(hào): LT3024EDE
廠商: LINEAR TECHNOLOGY CORP
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator
中文描述: DUAL OUTPUT, ADJUSTABLE POSITIVE LDO REGULATOR, PDSO12
封裝: 4 X 3 MM, 0.75 MM HEIGHT, PLASTIC, MO-229WGED, DFN-12
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 493K
代理商: LT3024EDE
13
LT3024
3024f
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capaci-
tor produced Figure 6’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
APPLICATIOU
W
U
U
For continuous normal conditions, the maximum junction
temperature rating of 125
°
C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. FE Package, 16-Lead TSSOP
COPPER AREA
TOPSIDE*
BACKSIDE
2500mm
2
2500mm
2
1000mm
2
2500mm
2
225mm
2
2500mm
2
100mm
2
2500mm
2
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
38
°
C/W
43
°
C/W
48
°
C/W
60
°
C/W
BOARD AREA
2500mm
2
2500mm
2
2500mm
2
2500mm
2
*Device is mounted on topside.
Table 2. UE Package, 12-Lead DFN
COPPER AREA
TOPSIDE*
BACKSIDE
2500mm
2
2500mm
2
1000mm
2
2500mm
2
225mm
2
2500mm
2
100mm
2
2500mm
2
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
40
°
C/W
45
°
C/W
50
°
C/W
62
°
C/W
BOARD AREA
2500mm
2
2500mm
2
2500mm
2
2500mm
2
*Device is mounted on topside.
The thermal resistance junction-to-case (
θ
JC
), measured
at the Exposed Pad on the back of the die is 10
°
C/W for the
DFN package and 8
°
C/W for the TSSOP package.
Calculating Junction Temperature
Example: Given Output 1 set for an output voltage of 3.3V,
Output 2 set for an output voltage of 2.5V, an input voltage
range of 3.8V to 5V, an output current range of 0mA to
500mA for Output 1, an output current range of 0mA to
100mA for Output 2 and a maximum ambient temperature
of 50
°
C, what will the maximum junction temperature be
100ms/DIV
3024 F05
V
500
μ
V/DIV
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
C
OUT
= 10
μ
F
C
BYP
= 0.01
μ
F
I
LOAD
= 100mA
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125
°
C). The
power dissipated by the device will be made up of two
components for each output:
1. Output current multiplied by the input/output voltage
differential: (I
OUT
)(V
IN
– V
OUT
), and
2. GND pin current multiplied by the input voltage:
(I
GND
)(V
IN
).
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance Char-
acteristics section. Power dissipation will be equal to the
sum of the two components listed above.
The LT3024 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
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