參數(shù)資料
型號: LTC1402IGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 10/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 2.2MSPS SHDN 16SSOP
標準包裝: 2,500
位數(shù): 12
采樣率(每秒): 2.2M
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 150mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
18
LTC1402
Figure 14. DSP Serial Interface to TMS320C54x
HARDWARE INTERFACE TO TMS320C54x
The LTC1402 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 14 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 2.2Msps conversion rate of the LTC1402.
The DSP assembly code sets frame sync mode at the BFSR
pin to accept an external positive going pulse, and the
serial clock at the BCLKR pin to accept an external positive
edge clock. Buffers near the LTC1402 may be added to
drive long tracks to the DSP to prevent corruption of the
signal to LTC1402. This configuration is adequate to
traverse a typical system board, but source resistors at the
buffer outputs, and termination resistors at the DSP may
be needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the DOUT
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 2.5V swing of the terminated transmission
lines. The OVDD supply output driver supply voltage can be
driven directly from the DSP.
APPLICATIONS INFORMATION
WU
U
1402 F14
11
16
15
10
9
3-WIRE SERIAL
INTERFACELINK
OVDD
CONV
SCK
LTC1402
DOUT
VCC
BFSR
BCLKR
TMS320C54x
BDR
OGND
CONV
CLK
5V
REF
B11
B10
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