Note 12: The absolute voltage at AIN+ and AIN– " />
參數(shù)資料
型號(hào)： LTC1402IGN#TRPBF
廠商： Linear Technology
文件頁數(shù)： 20/24頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 2.2MSPS SHDN 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 2.2M
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 150mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
5
LTC1402
Note 12: The absolute voltage at AIN+ and AIN– must be within this range.
Note 13: If less than 7.3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns)
because the 0.8ns delay through the sample-and-hold is subtracted from
the CONV to Hold mode delay.
Note 15: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
ELECTRICAL CHARACTERISTICS
Note 16: The time period for acquiring the input signal is started by the
14th rising clock and it is ended by the rising edge of convert.
Note 17: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10
F capacitive load. The
Sleep mode resets the REFREADY bit in the DOUT sequence. The
REFREADY bit goes high again 10ms after the VREF has stopped slewing in
wake up. This ensures valid REFREADY bit operation even with higher load
capacitances at VREF.
Note 18: The full power bandwidth is the frequency where the output code
swing drops to 2828LSBs with a 4VP-P input sine wave.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ENOBs and SINAD
vs Input Frequency (Bipolar)
SNR vs Input Frequency (Bipolar)
ENOBs and SINAD
vs Input Frequency (Unipolar)
SNR vs Input Frequency (Unipolar)
(Bipolar Mode Plots Run with Dual
±5V Supplies.
Unipolar Mode Plots Run with a Single 5V Supply. VDD = 5V, VSS = – 5V for Bipolar, VDD = 5V, VSS = 0V for Unipolar), TA = 25°C.
INPUT FREQUENCY (Hz)
104
105
106
107
4
EFFECTIVE
NUMBER
OF
BITS
SIGNAL-TO-NOISE
+
DISTORTION
(dB)
6
8
1401 G01
2
0
12
10
3
5
7
1
11
9
26
38
50
14
2
74
62
20
32
44
8
68
56
fSAMPLE = 2.22MHz
INPUT FREQUENCY (Hz)
104
105
106
107
–80
THD,
SFDR,
2ND
3RD
(dB)
–60
–40
1401 G02
–100
–120
0
–20
–90
–70
–50
–110
–10
–30
THD
SFDR
2ND
3RD
fSAMPLE = 2.22MHz
INPUT FREQUENCY (Hz)
104
105
106
107
–50
SNR
(dB) –38
–26
1401 G03
–62
–74
–2
–14
–56
–44
–32
–68
–8
–20
fSAMPLE = 2.22MHz
INPUT FREQUENCY (Hz)
104
105
106
107
4
EFFECTIVE
NUMBER
OF
BITS
SIGNAL-TO-NOISE
+
DISTORTION
(dB)
6
8
1401 G04
2
0
12
10
3
5
7
1
11
9
26
38
50
14
2
74
62
20
32
44
8
68
56
fSAMPLE = 2.22MHz
INPUT FREQUENCY (Hz)
104
105
106
107
–80
THD,
SFDR,
2ND
3RD
(dB)
–60
–40
1401 G05
–100
–120
0
–20
–90
–70
–50
–110
–10
–30
THD
SFDR
2ND
3RD
fSAMPLE = 2.22MHz
INPUT FREQUENCY (Hz)
104
105
106
107
–50
SNR
(dB) –38
–26
1401 G06
–62
–74
–2
–14
–56
–44
–32
–68
–8
–20
fSAMPLE = 2.22MHz
5 Harmonic THD, 2nd, 3rd and
SFDR vs Input Frequency
(Bipolar)
5 Harmonic THD, 2nd, 3rd and
SFDR vs Input Frequency
(Unipolar)
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