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參數(shù)資料
| 型號： | LTC1742CFW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SMPL 14BIT 65MSPS 48TSSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.38W |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
11
LTC1742
1742f
APPLICATIO S I FOR ATIO
WU
UU
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) FIN TJITTER
CONVERTER OPERATION
The LTC1742 is a CMOS pipelined multistep converter.
The converter has four pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later,
see the Timing Diagram section. The analog input is
differential for improved common mode noise immunity
and to maximize the input range. Additionally, the differen-
tial input drive will reduce even order harmonics of the
sample-and-hold circuit. The encode input is also
differential for improved common mode noise immunity.
The LTC1742 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
DIFF
REF
AMP
REF
BUF
4.7
F
1
F
0.1
F
0.1
F
1
F
INTERNAL CLOCK SIGNALS
REFL
REFH
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
2.35V
REFERENCE
FIRST PIPELINED
ADC STAGE
(5 BITS)
FOURTH PIPELINED
ADC STAGE
(4 BITS)
SECOND PIPELINED
ADC STAGE
(4 BITS)
ENC
REFHA
REFLB
REFLA REFHB
ENC
SHIFT REGISTER
AND CORRECTION
OE
MSBINV
OGND
OF
OVDD 0.5V TO
5V
D13
D0
CLKOUT
1742 F01
INPUT
S/H
SENSE
VCM
AIN
–
AIN
+
4.7
F
THIRD PIPELINED
ADC STAGE
(4 BITS)
OUTPUT
DRIVERS
CONTROL LOGIC
AND
CALIBRATION LOGIC
Figure 1. Functional Block Diagram
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