參數(shù)資料
型號(hào)： LTC1742CFW#TR
廠商： Linear Technology
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC SMPL 14BIT 65MSPS 48TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.38W
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 48-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
13
LTC1742
1742f
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1742 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100
or less for each input. The S/H
circuit is optimized for a 50
source impedance. If the
source impedance is less than 50
, a series resistor
should be added to increase this impedance to 50
. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC1742 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100
for each ADC input. A disadvantage of using a
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25
resistors and 12pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 100MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
Reference Operation
Figure 5 shows the LTC1742 reference circuitry consisting
of a 2.35V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V(
±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.35V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
APPLICATIO S I FOR ATIO
WU
UU
1:1
25
0.1
F
ANALOG
INPUT
VCM
AIN
+
AIN
–
100
100
12pF
1742 F03
4.7
F
25
25
25
LTC1742
25
5V
SINGLE-ENDED
INPUT
2.35V
±1/2
RANGE
VCM
AIN
+
AIN
–
12pF
1742 F04
4.7
F
25
100
500
500
25
25
LTC1742
–
+
1/2 LT1810
–
+
1/2 LT1810
Figure 4. Differential Drive with Op Amps
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
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