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參數(shù)資料
| 型號(hào)： | LTC1742CFW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SMPL 14BIT 65MSPS 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.38W |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
14
LTC1742
1742f
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry.
An external bypass capacitor is required for the 2.35V
reference output, VCM. This provides a high frequency low
impedance path to ground for internal and external cir-
cuitry. This is also the compensation capacitor for the
reference. It will not be stable without this capacitor.
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be con-
nected as shown in Figure 5.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1
F ceramic capacitor.
Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(> 40MHz), the 2V range will have the best SFDR perfor-
mance for the 2nd and 3rd harmonics, but the SNR will
degrade by 3.5dB. See the Typical Performance Charac-
teristics section.
Driving the Encode Inputs
The noise performance of the LTC1742 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
APPLICATIO S I FOR ATIO
WU
UU
VCM
REFHA
REFLB
SENSE
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 VSENSE FOR
1V < VSENSE < 1.6V
2.35V
REFLA
REFHB
4.7
F
4.7
F
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1
F
1742 F05
LTC1742
4
DIFF AMP
1
F
1
F
0.1
F
INTERNAL ADC
LOW REFERENCE
2.35V BANDGAP
REFERENCE
1.6V
1V
RANGE
DETECT
AND
CONTROL
Figure 5. Equivalent Reference Circuit
VCM
SENSE
2.35V
1.1V
4.7
F
12.5k
1
F
11k
1742 F06a
LTC1742
VCM
SENSE
2.35V
5V
1.25V
6
4
1, 2
4.7
F
1
F
0.1
F
1742 F06b
LTC1742
LT1790-1.25
Figure 6a. 2.2V Range ADC
Figure 6b. 2.5V Range ADC with External Reference
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