參數(shù)資料
型號(hào): LTC2158IUP-14#TRPBF
廠商: Linear Technology
文件頁數(shù): 13/28頁
文件大?。?/td> 0K
描述: IC ADC DUAL 14BIT 310M 64-QFN
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 310M
數(shù)據(jù)接口: 并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 873mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分
配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2158-14
20
215814f
applicaTions inForMaTion
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X indicates an unused bit that is read back as 0
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
SLEEP
NAP
PDB
0
Bits 7-4
Unused Bit
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1
PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused Bit
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUTdelayed by 45° (Clock Period 1/8)
10 = CLKOUT+/CLKOUTdelayed by 90° (Clock Period 1/4)
11 = CLKOUT+/CLKOUTdelayed by 135° (Clock Period 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
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