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參數(shù)資料
| 型號(hào)： | LTC2205CUK-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14-BIT 65MSPS 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 776mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2205-14
15
220514fb
CONVERTER OPERATION
The LTC2205-14 is a CMOS pipelined multi-step converter
with a front-end PGA. As shown in Figure 1, the converter
has ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205-14 has two phases of operation, determined
by the state of the differential ENC+/ENC– input pins. For
brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC, a
reconstruction DAC and a residue amplier. In operation,
the ADC quantizes the input to the stage, and the quantized
value is subtracted from the input by the DAC to produce a
residue. The residue is amplied and output by the residue
amplier. Successive stages operate out of phase so that
when odd stages are outputting their residue, the even
stages are acquiring that residue and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the voltage on the
sample capacitors is held. While ENC is high, the held
input voltage is buffered by the S/H amplier which drives
the rst pipelined ADC stage. The rst stage acquires
the output of the S/H amplier during the high phase of
ENC. When ENC goes back low, the rst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fth stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2205-14
CMOS differential sample and hold. The differential analog
inputs are sampled directly onto sampling capacitors
(CSAMPLE)throughNMOStransitors.Thecapacitorsshown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors which charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
Figure 2. Equivalent Input Circuit
APPLICATIONS INFORMATION
CSAMPLE
4.9pF
VDD
LTC2005-14
RPARASITIC
3Ω
RON
20Ω
RON
20Ω
RPARASITIC
3Ω
AIN+
220514 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2205CUK-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205CUK-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205CUK-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205IUK | 制造商:Linear Technology 功能描述:Single ADC Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP |
| LTC2205IUK#PBF | 制造商:Linear Technology 功能描述:Single ADC Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 16-bit, 65Msps ADC 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 65MSPS, QFN-48, Resolution (Bits):16bit, Sampling Rate:65MSPS, Supply Voltage Type:Single, Supply Voltage Min:3.135V, Supply Voltage Max:3.465V, Supply Current:185mA, Digital IC Case Style:QFN, No. of Pins:48 , RoHS Compliant: Yes |
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