OVDD V
參數(shù)資料
型號(hào)： LTC2207CUK-14#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/32頁(yè)
文件大小： 0K
描述： IC ADC 14BIT 105MSPS 48-QFN
標(biāo)準(zhǔn)包裝： 52
位數(shù)： 14
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.07W
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-QFN-EP（7x7）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
LTC2207-14/LTC2206-14
23
220714614fc
LTC2207-14/LTC2206-14
2207614 F11
OVDD
VDD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
33Ω
Figure 11. Equivalent Circuit for a Digital Output Buffer
DIGITAL OUTPUTS
Digital Output Buffers
Figure 11 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
eliminates the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2207-14/LTC2206-14 should drive
a minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required since
the output buffer has a series resistor of 33
Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
The LTC2207-14/LTC2206-14 parallel digital output can
be selected for offset binary or 2’s complement format.
The format is selected with the MODE pin. This pin has a
four level logic input, centered at 0, 1/3VDD, 2/3VDD and
VDD. An external resistor divider can be used to set the
1/3VDD and 2/3VDD logic levels. Table 1 shows the logic
states for the MODE pin.
Table 1. MODE Pin Function
MODE
OUTPUT FORMAT
CLOCK DUTY CYCLE STABILIZER
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
An overow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overow or underow.
Output Clock
The ADC has a delayed version of the encode input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the
Figure 12. Functional Equivalent of Digital Output Randomizer
CLKOUT+
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
D1
RAND = HIGH,
SCRAMBLE
ENABLED
D2
D12
D13
OF
LTC2207-14/LTC2206-14
CLKOUT
RAND
2207614 F12
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