參數(shù)資料
型號： LTC2207CUK-14#PBF
廠商： Linear Technology
文件頁數(shù)： 7/32頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 105MSPS 48-QFN
標準包裝： 52
位數(shù)： 14
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.07W
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN-EP（7x7）
包裝： 管件
輸入數(shù)目和類型： 1 個差分
配用： DC890B-ND - BOARD USB DATA COLLECTION
LTC2207-14/LTC2206-14
15
220714614fc
PIN FUNCTIONS
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under ow has occurred.
OE (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDDselects2’scomplement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 46): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA(Pin47):ProgrammableGainAmplierControlPin.Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
DITH
OE
MODE
PGA RAND
SHDN
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
ENC–
CORRECTION LOGIC
AND
SHIFT REGISTER
OGND
CLKOUT+
CLKOUT–
OF
D13
D12
OVDD
D1
D0
2207614 F01
INPUT
S/H
AIN
–
AIN
+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
VDD
GND
PGA
SENSE
VCM
BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
Figure 1. Functional Block Diagram
BLOCK DIAGRAM
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