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參數(shù)資料
| 型號(hào)： | LTC2207CUK-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 105MSPS 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.07W |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2207-14/LTC2206-14
17
220714614fc
CONVERTER OPERATION
The LTC2207-14/LTC2206-14 are CMOS pipelined
multistep converters with a front-end PGA. As
shown in Figure 1, the converter has ve pipelined
ADC stages; a sampled analog input will result in
a digitized value seven clock cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2207-14/LTC2206-14 have two phases of
operation, determined by the state of the differential
ENC+/ENC– input pins. For brevity, the text will refer to
ENC+ greater than ENC– as ENC high and ENC+ less than
ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages oper-
ate out-of-phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the Block Diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplier which
drives the rst pipelined ADC stage. The rst stage acquires
the output of the S/H amplier during the high phase of
ENC. When ENC goes back low, the rst stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fth
stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
APPLICATIONS INFORMATION
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| LTC2260IUJ-14#TRPBF | IC ADC 14BIT 105MSPS 40-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2207IUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP |
| LTC2207IUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 105MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 105MSPS 48QFN 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 105MSPS, QFN-48; Resolution (Bits):16bit; Sampling Rate:105MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:273mA; Digital IC Case Style:QFN; No. of Pins:48 ;RoHS Compliant: Yes |
| LTC2207IUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 105MSPS 48-QFN |
| LTC2207IUK-14 | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 14-bit Parallel 48-Pin QFN EP |
| LTC2207IUK-14#PBF | 功能描述:IC ADC 14BIT 105MSPS 48-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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