參數(shù)資料
型號(hào): LTC2223CUK
廠商: Linear Technology
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS SAMPLE 48QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 406mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2222/LTC2223
6
22223fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 105MHz (LTC2222) or 80MHz (LTC2223),
differential ENC+/ENC= 2VP-P sine wave, input range = 2VP-P with
differential drive, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LTC2222
LTC2223
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
l
1
105
1
80
MHz
tL
ENC Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
4.5
3
4.76
500
5.9
3
6.25
500
ns
tH
ENC High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
4.5
3
4.76
500
5.9
3
6.25
500
ns
tAP
Sample-and-Hold Aperture Delay
0
ns
tD
ENC to DATA Delay
(Note 7)
l
1.3
2.1
4
1.3
2.1
4
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
l
1.3
2.1
4
1.3
2.1
4
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
l
–0.6
0
0.6
–0.6
0
0.6
ns
tOE
Output Enable Delay
(Note 7)
l
5
10
5
10
ns
Pipeline Latency
5
Cycles
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
Note 5: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code ickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3.3V, fSAMPLE = 105MHz (LTC2222) or 80MHz (LTC2223),
differential ENC+/ENC= 2VP-P sine wave, input range = 1VP-P with
differential drive.
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