AIN+ (Pin 1): Positive Differential Analog Inp" />
參數(shù)資料
型號(hào): LTC2223CUK
廠商: Linear Technology
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS SAMPLE 48QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 406mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN-EP(7x7)
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,雙極; 1 個(gè)差分,雙極
LTC2222/LTC2223
13
22223fb
PIN FUNCTIONS
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
REFHA (Pins 3, 4): ADC High Reference. Bypass to Pins
5, 6 with 0.1μF ceramic chip capacitor, to Pins 9, 10 with a
2.2μF ceramic capacitor and to ground with a 1μF ceramic
capacitor.
REFLB (Pins 5, 6): ADC Low Reference. Bypass to Pins
3, 4 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 9, 10.
REFHB (Pins 7, 8): ADC High Reference. Bypass to Pins
9, 10 with 0.1μF ceramic chip capacitor. Do not connect
to Pins 3, 4.
REFLA (Pins 9, 10): ADC Low Reference. Bypass to Pins
7, 8 with 0.1μF ceramic chip capacitor, to Pins 3, 4 with a
2.2μF ceramic capacitor and to ground with a 1μF ceramic
capacitor.
VDD (Pins 11, 12, 14, 46, 47): 3.3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors. Adjacent pins
can share a bypass capacitor.
GND (Pins 13, 15, 45, 48): ADC Power Ground.
ENC+ (Pin 16):
Encode Input. The input is sampled on
the positive edge.
ENC(Pin 17):
Encode Complement Input. The input is
sampled on the negative edge. Bypass to ground with
0.1μF ceramic for single-ended ENCODE signal.
SHDN (Pin 18): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 19): Output Enable Pin. Refer to SHDN pin func-
tion.
CLOCKOUT (Pin 20): Data Valid Output. Latch data on the
falling edge of CLKOUT.
D0 – D11 (Pins 21, 24, 25, 26, 29, 30, 31, 34, 35, 36,
39, 40): Digital Outputs. D11 is the MSB.
OGND (Pins 22, 27, 32, 38): Output Driver Ground.
OVDD (Pins 23, 28, 33, 37): Positive Supply for the
Output Drivers. Bypass to ground with 0.1μF ceramic
chip capacitors.
OF (Pin 41): Over/Under Flow Output. High when an over
or under ow has occurred.
MODE (Pin 42): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3 VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3 VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 43): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 44): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered
to ground.
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