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參數(shù)資料
| 型號： | LTC2241CUP-10#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 210MSPS 64-QFN |
| 標準包裝： | 2,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 210M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 805mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2241-10
10
224110fb
PIN FUNCTIONS
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN– (Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins
7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12
with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins
5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins
11, 12 with 0.1μF ceramic chip capacitor. Do not connect
to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5,
6 with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17):
Encode Input. Conversion starts on the
positive edge.
ENC– (Pin 18):
Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1μF
ceramic for single-ended encode signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin function.
DNC (Pins 21, 22, 23, 24): Do not connect these pins.
D0–/D0+ to D9–/D9+ (Pins 27, 28, 29, 30, 31, 32, 37,
38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential
100Ω termination resistors at the LVDS receiver. D9–/D9+
is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Out-
put Drivers. Bypass to ground with 0.1μF ceramic chip
capacitor.
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid
Output. Latch data on rising edge of CLKOUT–, falling
edge of CLKOUT+.
OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under ow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demux CMOS mode with simultaneous
update. Connecting LVDS to 2/3VDD selects demux CMOS
mode with interleaved update. Connecting LVDS to VDD
selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. Connecting SENSE to VDD selects the internal
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±VSENSE. ±1V is the largest valid
input range.
VCM (Pin 60): 1.25V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
(LVDS Mode)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2241CUP-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-12#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 12BIT 210MSPS 64-QFN 制造商:Linear Technology 功能描述:IC, ADC, 12BIT, 210MSPS, QFN-64; Resolution (Bits):12bit; Sampling Rate:210MSPS; Supply Voltage Type:Single; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Supply Current:226mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2241CUP-12#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 12BIT 210MSPS 64-QFN |
| LTC2241CUP-12-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
| LTC2241CUP-12-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 210Msps ADC |
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