參數(shù)資料
型號(hào)： LTC2242IUP-10#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 7/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 250MSPS 64-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 10
采樣率（每秒）： 250M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 975mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
LTC2242-10
15
224210fd
applicaTions inForMaTion
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input is
held. While ENC is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H dur-
ing this high phase of ENC. When ENC goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When ENC goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third and fourth stages, resulting in a fourth stage residue
that is sent to the fifth stage ADC for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2242-10
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the
hold phase when ENC is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such
as the change seen with input frequencies near Nyquist,
then a larger charging glitch will be seen.
Common Mode Bias
For optimal performance the analog inputs should be
drivendifferentially.Eachinputshouldswing±0.5Vforthe
2V range or ±0.25V for the 1V range, around a common
mode voltage of 1.25V. The VCM output pin (Pin 60) may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set
the DC input level or as a reference level to an op amp
CSAMPLE
2pF
RON
14Ω
RON
14Ω
VDD
LTC2242-10
AIN+
224210 F02
CSAMPLE
2pF
VDD
AIN–
ENC–
ENC+
1.5V
6k
1.5V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
10Ω
Figure 2. Equivalent Input Circuit
相關(guān)PDF資料
PDF描述
VI-2NN-IX-B1 CONVERTER MOD DC/DC 18.5V 75W
MS27508E10B98S CONN RCPT 6POS BOX MNT W/SCKT
AD7886JP-REEL IC ADC 12BIT SAMPLING HS 28-PLCC
MS3106F20-23P CONN PLUG 2POS STRAIGHT W/PINS
LTC1385IG IC TXRX 3.3V EIA/TIA-562 20-SSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2242IUP-12 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 250Msps ADC
LTC2242IUP-12#PBF 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:Single ADC Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 12BIT 250MSPS 64-QFN 制造商:Linear Technology 功能描述:A/D Converter (A-D) IC 制造商:Linear Technology 功能描述:IC, ADC, 12BIT, 250MSPS, QFN-64, Resolution (Bits):12bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:2.375V, Supply Voltage Max:2.625V, Supply Current:285mA, Digital IC Case Style:QFN, No. of Pins:64 , RoHS Compliant: Yes 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 250Msps ADC
LTC2242IUP-12#TRPBF 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 12BIT 250MSPS 64-QFN
LTC2242UP-10 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:10-Bit, 250Msps ADC
LTC2242UP-12 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:12-Bit, 250Msps ADC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*