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參數(shù)資料
| 型號： | LTC2255IUH#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 125MSPS 3V 32-QFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2262 - Ultra Low Power High Speed ADCs |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 468mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極; 1 個差分，雙極 |
LTC2255/LTC2254
5
22554fa
TI I G CHARACTERISTICS
U
W
The
● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254),
input range = 2VP-P with differential drive, clock duty cycle stabilizer on,
unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2255) or 105MHz (LTC2254),
input range = 1VP-P with differential drive.
Note 9: Recommended operating conditions.
LTC2255
LTC2254
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
fs
Sampling Frequency
(Note 9)
●
1
125
1
105
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
●
3.8
4
500
4.5
4.76
500
ns
Duty Cycle Stabilizer On
●
3
4
500
3
4.76
500
ns
(Note 7)
tH
CLK High Time
Duty Cycle Stabilizer Off
●
3.8
4
500
4.5
4.76
500
ns
Duty Cycle Stabilizer On
●
3
4
500
3
4.76
500
ns
(Note 7)
tAP
Sample-and-Hold
0
ns
Aperture Delay
tD
CLK to DATA delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
1.4
2.7
5.4
ns
Data Access Time
CL = 5pF (Note 7)
●
4.3
10
4.3
10
ns
After OE
↓
BUS Relinquish Time
(Note 7)
●
3.3
8.5
3.3
8.5
ns
Pipeline Latency
5
Cycles
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