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參數(shù)資料
| 型號： | LTC2255IUH#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 125MSPS 3V 32-QFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2262 - Ultra Low Power High Speed ADCs |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 468mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，雙極; 1 個(gè)差分，雙極 |
LTC2255/LTC2254
14
22554fa
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2255/LTC2254 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and reac-
tance can influence SFDR. At the falling edge of CLK, the
sample-and-hold circuit will connect the 3.5pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100
or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2255/LTC2254 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Terminating on
the transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio trans-
former. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100
for
each ADC input. A disadvantage of using a transformer is
the loss of low frequency response. Most small RF trans-
formers have poor performance at frequencies below
1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
APPLICATIO S I FOR ATIO
WU
UU
Figure 5. Single-Ended Drive
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25
resistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4. Differential Drive with an Amplifier
25
25
25
25
0.1
F
AIN
+
AIN
–
12pF
2.2
F
VCM
LTC2255/
LTC2254
ANALOG
INPUT
0.1
FT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22554 F03
25
25
12pF
2.2
F
VCM
LTC2255/
LTC2254
22554 F04
–
+
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
AIN
+
AIN
–
25
0.1
F
ANALOG
INPUT
VCM
AIN
+
AIN
–
1k
12pF
224876 F05
2.2
F
1k
25
0.1
F
LTC2255/
LTC2254
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