參數(shù)資料
型號(hào)： LTC2264IUJ-12#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 17/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SER/PAR 40M 40-QFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： Serial LVDS
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 169mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN（6x6）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 Differential; 2 Single-Ended
配用： DC1371A-ND - BOARD USB DATA ACQUISITION HS
24
22654312fb
LTC2265-12/
LTC2264-12/LTC2263-12
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100 differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
Thedefaultoutputdrivercurrentis3.5mA.Thiscurrentcan
be adjusted by control register A2 in serial programming
mode.Availablecurrentlevelsare1.75mA,2.1mA,2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100 termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100 termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12).
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
65
4 fS
fS
8 fS
2-Lane
14-Bit Serialization
65
3.5 fS
0.5 fS
7 fS
2-Lane
12-Bit Serialization
65
3 fS
fS
6 fS
1-Lane
16-Bit Serialization
62.5
8 fS
fS
16 fS
1-Lane
14-Bit Serialization
65
7 fS
fS
14 fS
1-Lane
12-Bit Serialization
65
6 fS
fS
12 fS
APPLICATIONS INFORMATION
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
In addition to the 12 data bits (D11 - D0), two additional
bits (DX and DY) are sent out in the 14-bit and 16-bit
serialization modes. These extra bits are to ensure com-
plete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, DX and DY are always logic 0.
Whentheanaloginputsareoverrangedpositive,DXandDY
become logic 1. When the analog inputs are overranged
negative, DX and DY become logic 0. DX and DY can also
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
DX, DY
>+1.000000V
+0.999512V
+0.999024V
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1110
11
00
+0.000488V
0.000000V
–0.000488V
–0.000976V
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
00
–0.999512V
–1.000000V
≤–1.000000V
0000 0000 0001
0000 0000 0000
1000 0000 0001
1000 0000 0000
00
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