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參數(shù)資料
| 型號： | LTC2402 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10 |
| 中文描述： | 1-/2-Channel 24位ADC的無延遲uPower采用MSOP - 10 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 171K |
| 代理商： | LTC2402 |
11
LTC2401/LTC2402
APPLICATIOU
for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
The result of the first conversion on CH0 corresponds to
an input voltage of V
RTD
+ R1 I
EXCITATION.
The result of the
second conversion (CH1) is –R1 I
EXCITATION.
Note, the
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
–300mV to V
REF
+ 300mV. Adding the two conversion
results together, the voltage drop across the RTD’s leads
are cancelled and the final result is V
RTD
.
W
U
U
An Isolated, 24-Bit Data Acquisition System
The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.
+
+
F
O
SCK
SDO
CS
GND
V
CC
FS
SET
CH1
CH0
ZS
SET
LTC2402
24012 F09
LT1761-5
GND
10
μ
F
10V
TANT
10
μ
F
10V
TANT
+
10
μ
F
16V
TANT
+
10
μ
F
10V
TANT
10
μ
F
1
μ
F
T1
1/2 BAT54C
1/2 BAT54C
ISOLATION
BARRIER
= LOGIC COMMON
= FLOATING COMMON
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
1k
2
2
1
2
1
1
1
2
2
2
2
10
μ
F
CERAMIC
A
B
Y
Z
RO
RE
DE
DI
V
CC2
ST2
G1
V
CC1
G2
ST1
“SDO”
“SCK”
LOGIC 5V
IN
OUT
SHDN
BYP
LTC1535
Figure 9. Complete, Isolated 24-Bit Data Acquisition System
During power-up, the LTC2402 becomes active at V
CC
=
2.3V, while the isolated side of the LTC1535 must wait for
V
CC2
to reach its undervoltage lockout threshold of 4.2V.
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1k
pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1k
pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to V
CC1
until the LT1761’s
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facili-
tating communications with the LTC2402’s SDO output
without the need for any external components.
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| LTC2402CMSPBF | 制造商:Linear Technology 功能描述:ADC,LTC2402C 24bit D-S 2 ch SPI MSOP |
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