參數(shù)資料
型號: LTC2402
廠商: Linear Technology Corporation
英文描述: 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10
中文描述: 1-/2-Channel 24位ADC的無延遲uPower采用MSOP - 10
文件頁數(shù): 5/12頁
文件大小: 171K
代理商: LTC2402
5
LTC2401/LTC2402
V
CC
(Pin 1):
Positive Supply Voltage. Bypass to GND
(Pin4) with a 10
μ
F tantalum capacitor in parallel with
0.1
μ
F ceramic capacitor as close to the part as possible.
FS
SET
(Pin 2):
Full-Scale Set Input. This pin defines the
full-scale input value. When V
IN
= FS
SET
, the ADC outputs
full scale (FFFFF
H
). The total reference voltage is
FS
SET
– ZS
SET
.
CH0, CH1 (Pins 4, 3):
Analog Input Channels. The input
voltage range is –0.125 V
REF
to 1.125 V
REF
. For
V
REF
> 2.5V, the input voltage range may be limited by the
absolute maximum rating of –0.3V to V
CC
+ 0.3V. Conver-
sions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.
ZS
SET
(Pin 5):
Zero-Scale Set Input. This pin defines the
zero-scale input value. When V
IN
= ZS
SET
, the ADC
outputs zero scale (00000
H
).
GND (Pin 6):
Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single-point grounding system.
CS (Pin 7):
Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 8):
Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = V
CC
), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 9):
Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.
F
O
(Pin 10):
Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= 0V), the converter uses its internal oscillator
and the digital filter’s first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f
EOSC
/2560.
PI
FU
CTIO
N
S
U
U
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LTC2402C 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
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