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參數(shù)資料
| 型號(hào)： | LTC2402 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10 |
| 中文描述： | 1-/2-Channel 24位ADC的無(wú)延遲uPower采用MSOP - 10 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 171K |
| 代理商： | LTC2402 |
7
LTC2401/LTC2402
APPLICATIOU
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below –0.125 V
REF
, the conversion result is
clamped to the value corresponding to –0.125 V
REF
.
W
U
U
Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing
Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
Table 2. LTC2401/LTC2402 Output Data Format
Bit 31
Input Voltage
EOC
V
IN
> 9/8 V
REF
0
9/8 V
REF
0
V
REF
+ 1LSB
0
V
REF
0
3/4V
REF
+ 1LSB
0
3/4V
REF
0
1/2V
REF
+ 1LSB
0
1/2V
REF
0
1/4V
REF
+ 1LSB
0
1/4V
REF
0
0
+
/0
–
0
–1LSB
0
–1/8 V
REF
0
V
IN
< –1/8 V
REF
0
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
Bit 30
CH SELECT
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
CH0/CH1
Bit 29
SIG
1
1
1
1
1
1
1
1
1
1
1/0**
0
0
0
Bit 28
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
Bit 27
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 26
Bit 25
Bit 24
Bit 23
…
Bit 4
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
Bit 3-0
SUB LSBs*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
...
...
...
...
...
...
...
...
...
...
...
...
...
V
FULL-SCALE ERROR
SENSOR
SENSOR OUTPUT
R
P1
I
EXCITATION
+
–
V
OFFSET ERROR
+
–
+
–
R
P2
24012 F02
Figure 2. Errors Due to Excitation Currents
through the sensor. The wires connecting the sensor to the
ADC form parasitic resistors R
P1
and R
P2
. The excitation
current also flows through parasitic resistors R
P1
and R
P2
,
as shown in Figure 2. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.
In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a full-
scale set input (FS
SET
) and a zero-scale set input
(ZS
SET
). As shown in Figure 3, the FS
SET
pin acts as a zero
input full-scale sense input. Errors due to parasitic resis-
tance R
P1
in series with the half-bridge sensor are
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