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參數(shù)資料
| 型號： | LTC2413 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | ADC |
| 英文描述： | 2.7V to 5.5V Simultaneous 50Hz/60Hz Rejection Micropower Differential Σ△ Analog to Digital Converter(2.7V ～5.5V，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 2.7V至5.5V同步50Hz/60Hz抑制微差分Σ△模數(shù)轉(zhuǎn)換器（2.7?5.5V的，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 373K |
| 代理商： | LTC2413 |
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LTC2413
14
APPLICATIU
W
U
U
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC=0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result is
loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC=1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 26
μ
s
if the device is using its internal oscillator (F
0
= logic LOW).
If F
O
is driven by an external oscillator of frequency f
EOSC
,
Figure 7. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
2413 F07
MSB
SIG
BIT 8
BIT 27
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
GND
SDO
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
μ
F
2.7V TO 5.5V
LTC2413
= EXTERNAL OSCILLATOR
= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION
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