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參數(shù)資料
| 型號： | LTC2413 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | ADC |
| 英文描述： | 2.7V to 5.5V Simultaneous 50Hz/60Hz Rejection Micropower Differential Σ△ Analog to Digital Converter(2.7V ～5.5V，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 2.7V至5.5V同步50Hz/60Hz抑制微差分Σ△模數(shù)轉(zhuǎn)換器（2.7?5.5V的，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LTC2413 |
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LTC2413
18
APPLICATIU
W
U
U
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 12. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 13 and 14. Once the
voltage at CS falls below an internal threshold (
≈
1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 15 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
Figure 12. Internal Serial Clock, Autostart Operation
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2413 F12
BIT 0
SIG
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
EOC
BIT 31
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
GND
SDO
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1
μ
F
2.7V TO 5.5V
LTC2413
C
EXT
= EXTERNAL OSCILLATOR
= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION
2-WIRE I/O
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