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參數(shù)資料
| 型號： | LTC2413 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | ADC |
| 英文描述： | 2.7V to 5.5V Simultaneous 50Hz/60Hz Rejection Micropower Differential Σ△ Analog to Digital Converter(2.7V ～5.5V，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器) |
| 中文描述： | 2.7V至5.5V同步50Hz/60Hz抑制微差分Σ△模數(shù)轉(zhuǎn)換器（2.7?5.5V的，微功耗，24位差分Σ△串行模數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 22/40頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LTC2413 |
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LTC2413
22
APPLICATIU
W
U
U
For relatively small values of input capacitance (C
IN
<
0.01
μ
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
IN
will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C
IN
are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2413 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 18 and 19. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C
IN
values, the settling on IN
+
and IN
–
occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01
μ
F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When internal oscillator is used (F
O
= LOW), the typical
differential input resistance is 2M
which will generate a
gain error of approximately 0.25ppm for each ohm of
source resistance driving IN
+
or IN
–
. When F
O
is driven by
an external oscillator with a frequency f
EOSC
(external
conversion clock operation), the typical differential input
resistance is 0.28 10
12
/f
EOSC
and each ohm of
source resistance driving IN
+
or IN
–
will result in
1.78 10
–6
f
EOSC
ppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function
of the sum of the source resistance seen by IN
+
and IN
–
for
large values of C
IN
are shown in Figures 20 and 21.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
–
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
–
pins. When internal oscillator
is used (F
O
= LOW), every 1
mismatch in source imped-
ance transforms a full-scale common mode input signal
into a differential mode input signal of 0.25ppm. When F
O
is driven by an external oscillator with a frequency f
EOSC
,
every 1
mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 1.78 10
–6
f
EOSC
ppm. Figure 22
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN
+
and IN
–
pins when large C
IN
values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°
C) are
used for the external source impedance seen by IN
+
and
IN
–
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications a one-time cali-
bration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±
10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
μ
V typical and 1
μ
V maximum offset voltage.
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