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參數(shù)資料
| 型號(hào)： | LTC2489CDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，雙極；2 個(gè)差分，雙極 |
| 配用： | DC1010A-B-ND - BOARD DELTA SIGMA ADC LTC2489 |
LTC2489
8
2489fa
fO (Pin 1): Frequency Control Pin. Digital input that controls
the internal conversion clock rate. When fO is connected to
GND, the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the fO pin with an external clock in order to change
the output rate and the digital filter rejection null.
CA0, CA1 (Pins 2, 3): Chip Address Control Pins. These
pins are configured as a three-state (LOW, HIGH, Floating)
address control bits for the device’s I2C address.
SCL (Pin 4): Serial Clock Pin of the I2C Interface. The
LTC2489 can only act as a slave and the SCL pin only ac-
cepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
SDA (Pin 5): Bidirectional Serial Data Line of the I2C
Interface. In the transmitter mode (Read), the conver-
sion result is output through the SDA pin, while in the
receiver mode (Write), the device channel select bits are
input through the SDA pin. The pin is high impedance
during the data input mode and is an open drain output
(requires an appropriate pull-up device to VCC) during the
data output mode.
GND (Pin 6): Ground. Connect this pin to a common ground
plane through a low impedance connection.
COM (Pin 7): The Common Negative Input (IN–) for All
Single-Ended Multiplexer Configurations. The voltage
on CH0-CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN– ) provide a bipolar input
range (VIN = IN+ – IN– ) from –0.5 VREF to 0.5 VREF.
Outside this input range, the converter produces unique
over-range and under-range output codes.
CH0 to CH3 (Pin 8-Pin 11): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
REF+, REF– (Pin 13, Pin 14):
Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF = REF+
– REF–) sets the full-scale range for all input channels.
Exposed Pad (Pin 15): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
PIN FUNCTIONS
FUNCTIONAL BLOCK DIAGRAM
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
I2C
INTERFACE
GND
VCC
CH0
CH1
CH2
CH3
COM
MUX
IN+
IN–
CA0
SCL
REF+
REF–
CA1
SDA
fO
(INT/EXT)
2489 BD
+
–
1.7k
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