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參數(shù)資料
| 型號： | LTC4216 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Ultralow Voltage Hot Swap Controller |
| 中文描述： | 超低電壓熱插拔控制器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 277K |
| 代理商： | LTC4216 |
LTC4216
9
–
+
LOGIC
TIMER
TIMER
LTC4216**
SENSEP
V
CC
0.6V
V
IN
ON
FB
R4
R3
R
SENSE
R5
M2
M1
RESET
SENSEN
GATE
+
C1
C
LOAD
**ADDITIONAL DETAILS
OMITTED FOR CLARITY
RESET
μ
P
V
OUT
+
4216 F02
switch when the TIMER pin voltage exceeds its threshold.
The timer period for C1 to charge up to the TIMER pin
threshold, V
TMR(TH)
(1.253V), is given by:
For example, if C1 = 10nF, t
TIMER
= 6.2ms.
t
V C
A
μ
TIMER
=
1 253
1
2
.
(1)
FB Glitch Filtering
The FB pin is used to monitor the output voltage of the
external MOSFET through a resistive divider. Any tran-
sients on the FB pin due to the output low spikes will
pull
R
E
S
E
T low. To prevent
R
E
S
E
T from generating an
unwanted system reset, the FB comparator has a glitch
filter to ride out these glitches. The filter time is 20μs for
large transients (greater than 150mV) and up to 100μs
for small transients. The relationship between glitch filter
time and the FB pin transient voltage or FB overdrive is
shown in Figure 1.
FB pin voltage rises above 0.6V, the FB comparator output
goes low and a new timing cycle starts. After a complete
timing cycle at time point 6,
R
E
S
E
T is pulled high by the
external pull-up resistor, R5. The timer period given by
Equation (1) sets the power-good delay for
R
E
S
E
T going
high. If the FB pin voltage stays above 0.6V for less than
a timing cycle at time point 4, the
R
E
S
E
T output remains
low. Any overcurrent fault detected by the electronic circuit
breaker or
F
A
U
L
T pin driven low externally during the
timing cycle, will also pull the TIMER pin low and
R
E
S
E
T
output remains low.
When the device enters an undervoltage lockout condition
or the ON pin voltage drops below 0.4V,
R
E
S
E
T is pulled
low, ignoring the FB pin voltage.
Figure 2. Output Voltage Monitor Block Diagram
Figure 3. Output Voltage Monitor
Waveforms in Normal Operation
1 2
V
OUT
V
TMR(TH)
V
FB
< 0.6V
V
FB
> 0.6V
V
FB
< 0.6V
V
FB
> 0.6V
TIMER
RESET
GLITCH FILTER DELAY
3
4
5
6
POWER-GOOD
DELAY
2μA
2μA
4216 F03
APPLICATIU
W
U
U
Figure 1. FB Comparator Glitch Filter Time vs FB Overdrive
Output Voltage Monitor
As shown in Figure 2, the output voltage is monitored
through a resistive divider, R3 and R4, connected at the
FB pin, and a FB comparator with 0.6V threshold.
The normal operation of the output voltage monitor after a
start-up cycle is shown in Figure 3. At time point 1, when the
FB pin voltage falls below 0.6V, the FB comparator output
goes high.
R
E
S
E
T is pulled low by an internal N-channel
switch after a glitch filter delay at time point 2. When the
FB OVERDRIVE (mV)
0
100
120
140
160
120
80
60
40
80
200
40
20
0
G
μ
s
T
A
= 25
°
C
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