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參數(shù)資料
| 型號： | LTC4259A |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect |
| 中文描述： | 四IEEE 802.3af標準與AC電源斷開以太網(wǎng)控制器 |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LTC4259A |
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LTC4259A
26
4259Af
While it is sending its address, it monitors the SDAIN pin
to see if another device is sending an address at the same
time using standard I
2
C bus arbitration. If the LTC4259A
is sending a 1 and reads a 0 on the SDAIN pin on the rising
edge of SCL, it assumes another device with a lower
address is sending and the LTC4259A immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC4259A will
stop pulling down the INT pin. When the INT pin is released
in this way or if a 1 is written into the Clear Interrupt pin bit
(bit 6 of register 1Ah), the condition causing the LTC4259A
to pull the INT pin down must be removed before the
LTC4259A will be able to pull INT down again. This can be
done by reading and clearing the event registers or by
writing a 1 into the Clear All Interrupts bit (bit 7 of register
1Ah). The state of the INT pin can only change between I
2
C
transactions, so an interrupt is cleared or new interrupts
are generated after a transaction completes and before
new I
2
C bus communication commences. Periodic polling
of the alert response address can be used instead of the
INT pin if desired. If any device acknowledges the alert
response address, then the INT line, if connected, would
have been low.
System Software Strategy
Control of the LTC4259A hinges on one decision, the
LTC4259A’s operating mode. The three choices are de-
scribed under Operating Modes. In Auto mode the
LTC4259A can operate autonomously without direction
from a host controller. Because LTC4259As running in
Auto mode will power every valid PD connected to them,
the PSE must have 15.4W/port available. To reduce the
power requirements of the –48V supply, PSE systems
can track power usage, only turning on ports when
sufficient power is available. The IEEE describes this as a
power allocation algorithm and places two limitations: the
PSE shall not power a PD unless it can supply the
guaranteed power for that PD’s class (see Table 2) and
power allocation may not be based solely on a history of
APPLICATIOU
W
U
U
each PD’s power consumption. In order for a PSE to
implement power allocation, the PSE’s processor/con-
troller must control whether ports are powered—the
LTC4259A cannot be allowed to operate in Auto mode.
Semiauto mode fits the bill as the LTC4259A automati-
cally detects and classifies PDs, then makes this informa-
tion available to the host controller, which decides to
apply power or not. Operating the LTC4259A in Manual
mode also lets the controller decide whether to power the
ports but the controller must also control detection and
classification. If the host controller operates near the limit
of its computing resources, it may not be able to guide a
Manual mode LTC4259A through detect, class and port
turn-on in less than the IEEE mandated maximum of
950ms.
In a typical PSE, the LTC4259As will operate in Semiauto
mode as this allows the controller to decide to power a
port without unduly burdening the controller. With an
interrupt mask of F4h, the LTC4259A will signal to the
host after it has successfully detected and classed a PD,
at which point the host can decide whether enough power
is available and command the LTC4259A to turn that port
on. Similarly, the LTC4259A will generate interrupts when
a port’s power is turned off. By reading the LTC4259A’s
interrupt register, the host can determine if a port was
turned off due to overcurrent (t
START
or t
ICUT
faults) or
because the PD was removed (Disconnect event). The
host then updates the amount of available power to reflect
the power no longer consumed by the disconnected PD.
Setting the MSB of the interrupt mask causes the LTC4259A
to communicate fault conditions caused by failures within
the PSE, so the host does not need to poll to check that the
LTC4259As are operating properly. This interrupt driven
system architecture provides the controller with the final
say on powering ports at the same time, minimizing the
controller’s computation requirements because inter-
rupts are only generated when a PD is detected or on a
fault condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC4259A-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Synchronous No-Opto Flyback Controller |
| LTC4259ACGW | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#PBF | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#TR | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#TRPBF | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
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