
LTC4269-2
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An additional output signal is included for synchronous
rectifiercontroloractiveclampcontrol.Aprecision107mV
thresholdsensesovercurrentconditionsandtriggerssoft-
start for low stress short-circuit protection and control.
The key functions of the LTC4269-2 PWM controller are
shown in the Block Diagrams.
Part Start-Up
In normal operation, the SD_VSEC pin must exceed 1.32V
and the VIN pin must exceed 14.25V to allow the part
to turn on. This combination of pin voltages allows the
2.5V VREF pin to become active, supplying the LTC4269-2
control circuitry and providing up to 2.5mA external drive.
SD_VSECthresholdcanbeusedforexternallyprogramming
the power supply undervoltage lockout (UVLO) threshold
on the input voltage to the forward converter. Hysteresis
on the UVLO threshold can also be programmed since
the SD_VSEC pin draws 11A just before part turn-on and
0A after part turn-on.
With the LTC4269-2 turned on, the VIN pin can drop as
low as 8.75V before part shutdown occurs. This VIN pin
hysteresis (5.5V) combined with low 460A start-up input
current allows low power start-up using a resistor/capaci-
tor network from power supply input voltage to supply
the VIN pin (Figure 10). The VIN capacitor value is chosen
to prevent VIN falling below its turn-off threshold before
a bias winding in the converter takes over supply to the
VIN pin.
Output Drivers
The LTC4269-2 has two outputs, SOUT and OUT. The OUT
pin provides a ±1A peak MOSFET gate drive clamped to
13V. The SOUT pin has a ±50mA peak drive clamped to
12V and provides sync signal timing for synchronous
rectification control or active clamp control.
For SOUT and OUT turn-on, a PWM latch is set at the
start of each main oscillator cycle. OUT turn-on is delayed
from SOUT turn-on by a time, tDELAY (Figure 14). tDELAY
is programmed using a resistor from the DELAY pin to
GND and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by
one of three methods:
(1) MOSFET peak current sense at ISENSE pin
(2) Adaptive maximum duty cycle clamp reached during
load/line transients
(3) Maximum duty cycle reset of the PWM latch
During any of the following conditions—low VIN, low
SD_VSEC or overcurrent detection at the OC pin—a soft-
start event is latched and both SOUT and OUT turn off
immediately (Figure 11).
Leading Edge Blanking
To prevent MOSFET switching noise causing premature
turn-off of SOUT or OUT, programmable leading edge
blanking exists. This means both the current sense com-
parator and overcurrent comparator outputs are ignored
during MOSFET turn-on and for an extended period after
the OUT leading edge (Figure 12). The extended blanking
period is programmable by adjusting a resistor from the
BLANK pin to GND.
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
For forward converter applications, a maximum switch
duty cycle clamp which adapts to transformer input volt-
age is necessary for reliable control of the MOSFET. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can ex-
ceed the voltage rating of the primary-side MOSFETs with
catastrophic damage. Many converters solve this problem
by limiting the operational duty cycle of the MOSFET to
50%orless—orbyusingafixed(non-adaptive)maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LTC4269-2 provides a volt-second clamp to allow
MOSFET duty cycles well above 50%. This gives greater
power utilization for the MOSFETs, rectifiers and trans-
former resulting in less space for a given power output.
In addition, the volt-second clamp can allow a reduced
voltage rating on the MOSFET resulting in lower RDS(ON)
for greater efficiency. The volt-second clamp defines a
maximum duty cycle ‘guard rail’ which falls when power
supply input voltage increases.
applicaTions inForMaTion