參數(shù)資料
型號(hào): LTC6410IUD-6#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 0K
描述: IC AMP DIFF IF 16-QFN
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 差分
電路數(shù): 1
輸出類型: 差分
轉(zhuǎn)換速率: 1500 V/µs
-3db帶寬: 1.4GHz
電壓 - 輸入偏移: 400µV
電流 - 電源: 125mA
電流 - 輸出 / 通道: 42mA
電壓 - 電源,單路/雙路(±): 2.8 V ~ 5.5 V,±1.4 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
LTC6410-6
11
64106fa
APPLICATIONS INFORMATION
Introduction
The LTC6410-6 is a low noise differential high speed
amplier. By default, the LTC6410-6 has 6dB voltage gain
and is designed to operate with 50Ω differential input and
output impedances. By changing (REXT), alternative con-
gurations provide input resistances of up to 400Ω, with
correspondingly lower noise gure and higher power gain.
The Block Diagram shows the basic circuit along with key
external components while Table 1 provides conguration
information. If the input is AC-coupled, the VBIAS pin sets
the input common mode voltage and therefore the output
common mode voltage.
Input Impedance
LTC6410-6 has been designed with very exible input
termination circuitry. By default, with the termination pins
connected directly to the inputs, the input impedance is
58Ω, see the Block Diagram. Internally, there is 110Ω
between each input and the opposite output (RT). Divid-
ing the resistor by the internal noise gain of 2.7 + 1 = 3.7,
29.5Ω input impedance is created (59Ω differential ). In
parallel with the 2k common mode resistance, a total of
58Ω differential input impedance is achieved. This method
of termination is used to provide lower noise gure through
the use of feedback which reduces the effective noise of
the termination resistor. By adding additional resistance in
series with the termination pins, higher input impedances
can be obtained (see Table 1). The optimum impedance
for minimizing the noise gure of the LTC6410-6 is close
to 400Ω. Because the amplier is inherently a voltage
amplier, the difference between the impedance at the
input and the output adds additional power gain as can
be seen in Table 1. These higher impedance levels can be
useful in interfacing with active mixers which can have
output impedance of 400Ω and beyond.
Input and Output Common Mode Bias
The LTC6410-6 is internally self-biased through the VBIAS
pin (see the Block Diagram). Therefore the LTC6410-6
can be AC-coupled with no external biasing circuitry. The
output will have approximately the same common mode
voltage as the input.
In the case of a DC-coupled input connection, the input
DC common mode voltage will also set the output com-
mon mode voltage. Note that a voltage divider is formed
between the VBIAS buffer output and the DC input source
impedance.
The VBIAS pin has an internal voltage divider which will
self bias to approximately 1.4V on a 3V supply (0.47
VSUPPLY). An external capacitor of 0.1μF to ground is
recommended to bypass the pin. The resistance of the pin
is 3k. See Distortion vs Common Mode graph.
For increased common mode accuracy, the +TERM and
–TERM pins can be AC-coupled to the inputs with capaci-
tors (CEXT). This coupling prevents the feedback from the
termination resistance from creating additional DC com-
mon mode voltage error. The GCM and VOSCM of the DC
Electrical Characteristics table reect the less accurate
DC-coupled scenario.
The termination inputs are part of a high speed feedback
loop. The physical length of the termination loop (REXT
and CEXT) must be minimized to maintain stability and
minimize gain peaking.
Gain
Internally, the LTC6410-6 has a voltage gain of 2.7V/V.
The default source and load resistances in most of the
data sheet are assumed to be 50Ω differential. Due to the
input and output resistance of the LTC6410-6 being 58Ω
and 22Ω respectively, the overall voltage gain in a 50Ω
system is 6dB (2V/V). Other source and load resistances
will produce different gains due to the resistive dividers.
Figure 1 is a system diagram for calculating gain.
Figure 1
RIN
64106 F01
RS
RLOAD
LTC6410-6
ROUT
22Ω
VS
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