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參數(shù)資料
| 型號(hào)： | LU6612 |
| 英文描述： | LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX |
| 中文描述： | LU6612 FASTCAT商標(biāo)單的10BASE-T/100BASE-TX快速以太網(wǎng)場(chǎng)效應(yīng)管 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 528K |
| 代理商： | LU6612 |
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LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet
July 2000
16
Lucent Technologies Inc.
MII Station Management
(continued)
Table 10. MR1—Status Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Bit
1
Type
2
R
Description
1.15 (T4ABLE)
100Base-T4 Ability.
This bit will always be a 0.
0: Not able
1: Able
100Base-TX Full-Duplex Ability.
This bit will always be a 1.
0: Not able
1: Able
100Base-TX Half-Duplex Ability.
This bit will always be a 1.
0: Not able
1: Able
10Base-T Full-Duplex Ability.
This bit will always be a 1.
0: Not able
1: Able
10Base-T Half-Duplex Ability.
This bit will always be a 1.
0: Not able
1: Able
Reserved.
All bits will read as a 0.
Suppress Preamble.
This bit is set to a 1, indicating that the LU6612 accepts
management frames with the preamble suppressed. (This function is not sup-
ported by QS6611.)
Autonegotiation Complete.
When this bit is a 1, it indicates the autonegotiation
process has been completed. The contents of registers MR4, MR5, MR6, and
MR7 are now valid. The default value is a 0. This bit is reset when autonegotia-
tion is started.
Remote Fault.
When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. The default is a 0.
Autonegotiation Ability.
When this bit is a 1, it indicates the ability to perform
autonegotiation. The value of this bit is always a 1.
Link Status.
When this bit is a 1, it indicates a valid link has been established.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.
Jabber Detect.
This bit will be a 1 whenever a jabber condition is detected. It will
remain set until it is read, and the jabber condition no longer exists.
Extended Capability.
This bit indicates that the LU6612 supports the extended
register set (MR2 and beyond). It will always read a 1.
1.14 (TXFULDUP)
R
1.13 (TXHAFDUP)
R
1.12 (ENFULDUP)
R
1.11 (ENHAFDUP)
R
1.10:7
R
R
1.6 (NO_PA_OK)
1.5 (NWAYDONE)
R
1.4 (REM_FLT)
R
1.3 (NWAYABLE)
R
1.2 (LSTAT_OK)
R
1.1 (JABBER)
R
1.0 (EXT_ABLE)
R
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