L8575
Dual-Resistive, Low-Cost SLIC
Advance Data Sheet
March 1997
32
Lucent Technologies Inc.
ac Design
(continued)
Design Equations
(continued)
To scale C
S
(higher), increase C
T
(and decrease R
T2
)
by increasing the R
GX1
/ (R
GX1
+ R
T1
) ratio by rearrang-
ing the circuit in Figure 13 and by adding resistor R
SC
from XMT to IRP as shown in the figure below:
12-3427a(F)
Figure 15. Addition of Resistor R
SC
from XMT to IRP
Then,
Once the gains and complex termination are set, if the
hybrid balance network is identical to the termination
impedance, then the hybrid balance is set by a single
resistor (shown in Figure 15) and is computed as fol-
lows:
The L8575 SLIC is ground referenced. However, a +5 V
only codec, such as T7504, is referenced to +2.5 V. The
L8575 SLIC has sufficient dynamic range to accommo-
date an ac signal from the codec that is referenced to
+2.5 V without clipping distortion.
With a –48 V battery, the dc voltage at node XMT will
be a nominal –22 V or
common-mode dc voltage. This will cause a dc current
flow from the codec to the SLIC. This current will not
affect ac performance, but it will effectively waste
power. To avoid this wasted power consumption, block-
ing capacitors can be added. The blocking capacitors
block the dc path from any low impedance node at the
codec to SLIC node XMT. Blocking capacitors are
added to the application diagram in Figure 16.
– 4 V. This is the
After the blocking capacitor C
B
is added, the above
component values may have to be adjusted slightly to
optimize performance.
The effects of the blocking capacitor are best evaluated
and optimized by circuit simulation. Contact your
Lucent Technologies Microelectronics Group Account
Representative for information on availability of a
PSPICE* model.
Figure 16 shows a complete reference design using the
L8575 SLIC and T8502/3 codec. This line circuit is
designed to meet the requirements of the People’s
Republic of China. The basic ac design parameters are
listed below:
Termination impedance: 200
+ 680
||
0.1
μ
F
Hybrid balance network: 200
+ 680
||
0.1
μ
F
Transmit gain: 0 dB
Receive gain: –3.5 dB or –7.0 dB
Notice that the interface circuit between the L8575 and
T8502/3 is designed for a receive gain of –3.5 dB.
The T8502 codec offers a pin selectable receive gain of
0 dB or –3.5 dB. Thus, via logic control, a receive gain
of either –3.5 dB or 7.0 dB is achieved.
The T8502/3 codec is a dual +5 V only codec. When
used with the dual L8575 SLIC, a complete low-cost,
dual-line circuit is achieved.
*PSPICEis a registered trademark of MicroSim Corporation.
R
T1
R
SC
IRP
C
T
R
T2
XMT
VRN
R
GX1
C
B
GX1
R
GX1
R
T1
+
--------R
||
------------------------------------
)
600
--1
1
′
---------
–
RV1
+
R
RV1
R
SC
-------R
+
=
R
HB
--------------------------------
=
----------------------------------------
)