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參數(shù)資料
| 型號(hào)： | LVX259 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 114K |
| 代理商： | LVX259 |
MC74LVX259
http://onsemi.com
5
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
T
A
= 25
°
C
40
°
C
≤
T
A
≤
85
°
C
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
V
IH
Minimum HighLevel
Input Voltage
2.0
3.0
3.6
0.75 V
CC
0.7 V
CC
0.7 V
CC
0.75 V
CC
0.7 V
CC
0.7 V
CC
V
V
IL
Maximum LowLevel
Input Voltage
2.0
3.0
3.6
0.25 V
CC
0.3 V
CC
0.3 V
CC
0.25 V
CC
0.3 V
CC
0.3 V
CC
V
V
OH
HighLevel Output
Voltage
I
OH
= 50 A
2.0
1.9
2.0
1.9
V
I
OH
= 50 A
3.0
2.9
3.0
2.9
I
OH
= 4 mA
3.0
2.58
2.48
V
OL
LowLevel Output
Voltage
I
OL
= 50 A
2.0
0.0
0.1
0.1
V
I
OL
= 50 A
3.0
0.0
0.1
0.1
I
OL
= 4 mA
3.0
0.36
0.44
I
IN
Input Leakage Current
V
IN
= 5.5 V or GND
0 to 3.6
±
0.1
±
1.0
A
I
CC
Maximum Quiescent
Supply Current
(per package)
V
IN
= V
CC
or GND
3.6
1.0
1.0
2.0
A
to Output
r
f
Typical @ 25
°
C, V
CC
= 3.3 V
A
1.0
A
t
PHL
to Output
(Figures 6 and 9)
Delay, Data to Output
(Figures 5 and 9)
(Figures 5 and 9)
Maximum Propagation
V
C
= 50pF
12.0
9.0
14.0
1.0
15.0
pF
Delay, Reset to Output
(Figures 7 and 9)
(Figures 7 and 9)
C
L
= 50pF
14.0
1.0
14.0
t
PLH
,
Maximum Propagation
V
CC
= 2.7 V
C
L
= 15pF
L
6.3
14.0
9.0
1.0
15.0
12.0
ns
V
CC
L
C
= 50pF
5.6
1.0
11.0
C
IN
Maximum Input
t
PHL
Delay, Enable to Output
C
L
= 50pF
9.0
1.0
15.0
V
CC
= 3.3 V
±
0.3 V
C
L
= 15pF
C
L
= 50pF
PHL
Maximum Propogation
V
CC
L
C
= 50pF
12.0
1.0
1.0
14.0
10
15.0
C
L
= 50pF
10
6
C
PD
Power Dissipation Capacitance (Note 5)
5. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the noload dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
30
pF
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