LXT381 —
Octal E1 Line Interface Unit
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Datasheet
Figures
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LXT381 144-Pin Low-Profile Quad Flat Package (LQFP) Pin Assignments and
Package Markings5
LXT381 160-Pin Plastic Ball Grid Array (PBGA) Pin Assignments.......................6
Analog Loopback ................................................................................................15
Remote Looback.................................................................................................15
External Transmit/Receive Line Circuitry...........................................................17
LXT381 JTAG Architecture .................................................................................18
JTAG State Diagram...........................................................................................20
Analog Test Port Application..............................................................................26
Transmit Clock Timing ........................................................................................30
Receive Timing Diagram.....................................................................................31
JTAG Timing .......................................................................................................31
E1 Mask Templates ............................................................................................33
LXT381 144 Pin LQFP Package Dimensions .....................................................34
LXT381 160 Pin PBGA Package Dimensions.....................................................35
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Tables
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LXT381 Pin Description ........................................................................................7
Operation Mode Summary..................................................................................16
TAP State Description.........................................................................................19
Boundary Scan Register (BSR) ..........................................................................21
Device Identification Register (IDR)....................................................................24
Analog Port Scan Register (ASR).......................................................................24
Instruction Register (IR) ......................................................................................26
Absolute Maximum Ratings ................................................................................27
Recommended Operating Conditions.................................................................27
Transmit Transmission Characteristics...............................................................28
DC Characteristics..............................................................................................28
Receive Transmission Characteristics................................................................29
Analog Test Port Characteristics.........................................................................30
Transmit Timing Characteristics..........................................................................30
Receive Timing Characteristics...........................................................................30
JTAG Timing Characteristics ..............................................................................31
Transformer Specifications .................................................................................32
G.703 2.048 Mbit/s Pulse Mask Specifications...................................................32