參數(shù)資料
型號(hào)： LXT381BE
廠(chǎng)商： INTEL CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： Octal E1 Line Interface Unit
中文描述： DATACOM, PCM TRANSCEIVER, PBGA160
封裝： PLASTIC, BGA-160
文件頁(yè)數(shù)： 8/36頁(yè)
文件大小： 218K
代理商： LXT381BE
LXT381
—
Octal E1 Line Interface
8
Datasheet
14
F3
GND
S
Ground.
This pin must be connected to Ground.
15
F4
GND
S
Ground.
This pin must be connected to Ground.
16
G3
GND
S
Ground.
This pin must be connected to Ground.
17
G1
VCCIO0
S
Power (I/O).
18
G4
GNDIO0
S
Ground (I/O).
19
H1
VCC0
S
Power (Core).
20
H4
GND0
S
Ground (Core).
21
22
23
24
25
26
27
28
G2
H3
H2
J4
J3
J2
J1
K1
LOOP0
LOOP1
LOOP2
LOOP3
LOOP4
LOOP5
LOOP6
LOOP7
DI
DI
DI
DI
DI
DI
DI
DI
Loopback Mode Select/Parallel Databus Input & Output.
These pins
are inputs that select the loopback mode for transceiver ports 0-7
respectively as follows:
Normal operation (no loopback) is selected when pin is left open
(unconnected).
Remote loopback mode is selected when pin is Low. In this mode, data on
TPOS and TNEG is ignored and data received on RTIP and RRING is
looped around and retransmitted on TTIP and TRING.
Analog local loopback mode is selected when pin is High. In this mode,
data received on RTIP and RRING is ignored and data transmitted on TTIP
and TRING is internally looped around and routed back to the receive
inputs.
Note:
When these inputs are left open, they stay in a high impedance
state. Therefore, the layout design should not route signals with fast
transitions near the LOOP pins. This practice will minimize
capacitive coupling.
29
L1
TCLK1
DI
Transmit Clock Input.
30
31
L2
L3
TPOS1
TNEG1
DI
DI
Transmit Positive Data Input.
Transmit Negative Data Input.
32
M1
RCLK1
DO
Receive Clock Output.
33
34
M2
M3
RPOS1
RNEG1
DO
DO
Receive Positive Data Output.
Receive Negative Data Output.
35
K3
ALOS1
DO
Analog Loss of Signal Output.
36
N1
TCLK0
DI
Transmit Clock Input.
37
38
N2
N3
TPOS0
TNEG0
DI
DI
Transmit Positive Data Input.
Transmit Negative Data Input.
39
P1
RCLK0
DO
Receive Clock Output.
40
41
P2
P3
RPOS0
RNEG0
DO
DO
Receive Positive Data.
Receive Negative Data.
42
K4
ALOS0
DO
Analog Loss of Signal Output.
43
K2
GND
S
Ground.
This pin must be connected to Ground.
44
N4, P4
TVCC0
S
Transmit Driver Power Supply.
Power supply pin for the output driver.
Table 1. LXT381 Pin Description (Continued)
Pin #
LQFP
Pin #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not
Connected.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT381LE 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:Octal E1 Line Interface Unit
LXT384/LXT386/LXT388 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LXT384/LXT386/LXT388 - LXT384/6/8 Twisted Pair Interface Without Component Changes
LXT384BE 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Telecomm/Datacomm
LXT384LE 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Telecomm/Datacomm
LXT386 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver
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