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參數(shù)資料
| 型號： | M1026-1Z-168.0400 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開發(fā)出復(fù)雜基于時(shí)鐘鎖相環(huán)AUTOSWITCH |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 322K |
| 代理商： | M1026-1Z-168.0400 |
M1025/26 Datasheet Rev 1.0
3
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Tables
3
and
4 respectively
.
M1025 M/R Divider LUT
ables 3 and
4
provide example Fin and phase
detector frequencies with
155.52MHz
VCSO
devices (
M1025-11-155.5200
and
M1026-11-155.5200
).
See “Ordering Information” on pg. 14
.
M1026 M/R Divider LUT
Phase
Locked
Loop
(PLL)
M1025/26
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
PLL
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
M Divider
NBW
R
IN
R
IN
M / R Divider
LUT
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL
Phase
Detector
REF_ACK
AUTO
LOL
nFOUT
P_SEL1:0
P Divider
LUT
(1, 2, or TriState)
4
2
TriState
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
19.44
4.86
1.215
0.30375
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
8
1
4
8
8
8
8
2
2
2
2
1
1
1
1
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
32
128
512
2
8
32
128
1
4
16
64
Test Mode
1
1
4
16
16
64
1
4
16
64
1
4
16
64
Note 1: Factory test mode; do not use.
N/A
0.25
0.25
0.25
4
16
64
Table 3: M1025 M/R Divider LUT
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
38.88
9.72
2.43
0.6075
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
4
1
4
4
4
4
4
2
2
2
2
1
1
1
1
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
16
64
256
2
8
32
128
1
4
16
64
Test Mode
1
1
4
16
16
64
1
4
16
64
1
4
16
64
Note 1: Factory test mode; do not use.
N/A
0.25
0.25
0.25
4
16
64
Table 4: M1026 M/R Divider LUT
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| M1026-1Z-172.6423 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
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