參數(shù)資料
型號: M12L64322A-5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 4.5 ns, PBGA90
封裝: 8 X 13 MM, LEAD FREE, BGA-90
文件頁數(shù): 31/47頁
文件大?。?/td> 791K
代理商: M12L64322A-5BG
ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
31/47
Note :
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1
BA0
Active & Read/Write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA1
BA0
Operating
0
0
Disable auto precharge, leave A bank active at end of burst.
0
1
Disable auto precharge, leave B bank active at end of burst.
1
0
Disable auto precharge, leave C bank active at end of burst.
0
1
1
Disable auto precharge, leave D bank active at end of burst.
0
0
Enable auto precharge , precharge bank A at end of burst.
0
1
Enable auto precharge , precharge bank B at end of burst.
1
0
Enable auto precharge , precharge bank C at end of burst.
1
1
1
Enable auto precharge , precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
X
X
All Banks
相關(guān)PDF資料
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