參數(shù)資料
型號: M12L64322A-6BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝: 8 X 13 MM, LEAD FREE, BGA-90
文件頁數(shù): 25/47頁
文件大小: 791K
代理商: M12L64322A-6BG
ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
25/47
10. Clock Suspend Exit & Power Down Exit
1) Cl o c k S u s p en d ( = Ac t iv e P ow er D o wn ) E x i t
11. Auto Refresh & Self Refresh
*Note
:
1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During t
RC
from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of t
RC
from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (40% cycles) is recommended.
CLK
CKE
Internal
CLK
C M D
R D
t
S S
*Not e 1
CLK
CKE
Internal
CLK
C M D
AC T
t
S S
*Not e 2
NOP
2) P ow er D ow n ( = P r ec h a r g e P o w e r Do w n )
C L K
C M D
P R E
A R
C K E
C M D
t
R P
t
R C
* N o t e 5
* N o t e 4
C L K
C M D
P R E
S R
C K E
C M D
t
R P
t
R C
* N o t e 4
1 ) A u t o R e f r e s h & S e l f R e f r e s h
* N o t e 3
2 ) S e l f R e f r e s h
* N o t e 8
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