參數(shù)資料
型號(hào): M12L64322A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 512K x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 X 0.875 INCH, 0.50 MM PITCH, LEAD FREE, TSOP2-86
文件頁數(shù): 44/47頁
文件大?。?/td> 791K
代理商: M12L64322A-6TG
ES MT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2007
Revision
:
2.3
44/47
Mode Register Set Cycle
Auto Refresh Cycle
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , &
WE
activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
:Don't Car e
HIGH
0 1 2 3 4 5 6
0 1 2 3 4 5 6 7 8 9 10
HIGH
Key
Ra
HI- Z
HI- Z
*Not e 2
*N ot e 1
*N ot e 3
t
R C
M R S
New
Command
Auto Refresh
New Com m an d
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