- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377801 > M12S64322A (Elite Semiconductor Memory Technology Inc.) 512K x 32 Bit x 4 Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | M12S64322A |
| 廠商： | Elite Semiconductor Memory Technology Inc. |
| 英文描述： | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 為512k × 32位× 4個銀行同步DRAM |
| 文件頁數(shù)： | 42/46頁 |
| 文件大小： | 746K |
| 代理商： | M12S64322A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁
ES MT
M12S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision
:
1.0
42/46
Self Refresh Entry & Exit Cycle
*Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum t
RC
is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
BA 0, BA 1
S el f R ef r es h E n t r y
A u t o R ef r es h
: D o n ' t c a r e
*Not e 2
*Not e 1
t
S S
*No t e 3
*Not e 4
t
R C
m i n
*Not e 6
S e l f R ef r e s h E xi t
H i - Z
H i - Z
*No t e 5
*Not e 7
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12S64322A-6BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M13S128168A | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12S64322A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。