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參數(shù)資料
| 型號(hào)： | M1AFS250-FFG256 |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 250000 GATES, PBGA256 |
| 封裝： | 1.0 MM PITCH, BGA-256 |
| 文件頁(yè)數(shù)： | 158/318頁(yè) |
| 文件大?。?/td> | 10129K |
| 代理商： | M1AFS250-FFG256 |
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Device Architecture
2- 224
Pr el iminar y v1 .7
AES decryption can also be used on the 1,024-bit FlashROM to allow for secure remote updates of
the FlashROM contents. This allows for easy, secure support for subscription model products. See
the application note Fusion Security for more details.
AES for Flash Memory
AES decryption can also be used on the flash memory blocks. This allows for the secure update of
the flash memory blocks. During runtime, the encrypted data can be clocked in via the JTAG
interface. The data can be passed through the internal AES decryption engine, and the decrypted
data can then be stored in the flash memory block.
Programming
Programming can be performed using various programming tools, such as Silicon Sculptor II (BP
Micro Systems) or FlashPro3 (Actel).
The user can generate STP programming files from the Designer software and can use these files to
program a device.
Fusion devices can be programmed in-system. During programming, VCCOSC is needed in order to
power the internal 100 MHz oscillator. This oscillator is used as a source for the 20 MHz oscillator
that is used to drive the charge pump for programming.
ISP
Fusion devices support IEEE 1532 ISP via JTAG and require a single VPUMP voltage of 3.3 V during
programming. In addition, programming via a microcontroller in a target system can be achieved.
Refer to the standard or the In-System Programming (ISP) of Actel's Low-Power Flash Devices Using
FlashPro3 document for more details.
JTAG IEEE 1532
Programming with IEEE 1532
Fusion devices support the JTAG-based IEEE1532 standard for ISP. As part of this support, when a
Fusion device is in an unprogrammed state, all user I/O pins are disabled. This is achieved by
keeping the global IO_EN signal deactivated, which also has the effect of disabling the input
buffers. Consequently, the SAMPLE instruction will have no effect while the Fusion device is in this
unprogrammed state—different behavior from that of the ProASICPLUS device family. This is done
because SAMPLE is defined in the IEEE1532 specification as a noninvasive instruction. If the input
buffers were to be enabled by SAMPLE temporarily turning on the I/Os, then it would not truly be
a noninvasive instruction. Refer to the standard or the In-System Programming (ISP) of Actel's Low-
Power Flash Devices Using FlashPro3 document for more details.
Boundary Scan
Fusion devices are compatible with IEEE Standard 1149.1, which defines a hardware architecture
and the set of mechanisms for boundary scan testing. The basic Fusion boundary scan logic circuit is
composed of the test access port (TAP) controller, test data registers, and instruction register
(Figure 2-138 on page 2-226). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and the optional IDCODE instruction (Table 2-182 on page 2-226).
Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input),
TDI, TDO (test data input and output), TMS (test mode selector), and TRST (test reset input). TMS,
TDI, and TRST are equipped with pull-up resistors to ensure proper operation when no input data is
supplied to them. These pins are dedicated for boundary scan test usage. Refer to the "JTAG Pins"
section on page 2-221 for pull-up/-down recommendations for TDO and TCK pins. The TAP
controller is a 4-bit state machine (16 states) that operates as shown in Figure 2-138 on page 2-226.
The 1s and 0s represent the values that must be present on TMS at a rising edge of TCK for the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1AFS250-FFGG256 | FPGA, 250000 GATES, PBGA256 |
| M1AFS250-FPQ208 | FPGA, 250000 GATES, PQFP208 |
| M1AFS250-FPQG208 | FPGA, 250000 GATES, PQFP208 |
| M1AFS250-FQN180 | FPGA, 250000 GATES, PBCC180 |
| M1AFS250-FQNG180 | FPGA, 250000 GATES, PBCC180 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS250-FFG256ES | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFG256I | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFG256PP | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFGG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays |
| M1AFS250-FFGG256ES | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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