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參數(shù)資料
| 型號： | M1AFS250-FFG256 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 250000 GATES, PBGA256 |
| 封裝： | 1.0 MM PITCH, BGA-256 |
| 文件頁數(shù)： | 275/318頁 |
| 文件大小： | 10129K |
| 代理商： | M1AFS250-FFG256 |
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Fusion Device Family Overview
1- 2
Prel i minary v1 .7
user with a high level of flexibility and integration to support a wide variety of mixed-signal
applications. The flash memory block capacity ranges from 2 Mbits to 8 Mbits. The integrated 12-
bit ADC supports up to 30 independently configurable input channels. The on-chip crystal and RC
oscillators work in conjunction with the integrated phase-locked loops (PLLs) to provide clocking
support to the FPGA array and on-chip resources. In addition to supporting typical RTC uses such as
watchdog timer, the Fusion RTC can control the on-chip voltage regulator to power down the
device (FPGA fabric, flash memory block, and ADC), enabling a low-power standby mode.
The Actel Fusion family offers revolutionary features, never before available in an FPGA. The
nonvolatile flash technology gives the Fusion solution the advantage of being a secure, low-power,
single-chip solution that is live at power-up. Fusion is reprogrammable and offers time to market
benefits at an ASIC-level unit cost. These features enable designers to create high-density systems
using existing ASIC or FPGA design flows and tools.
The family has up to 1.5 M system gates, supported with up to 270 kbits of true dual-port SRAM, up
to 8 Mbits of flash memory, 1 kbit of user FlashROM, and up to 278 user I/Os. With integrated flash
memory, the Fusion family is the ultimate soft-processor platform. The AFS600 and AFS1500 devices
both support the Actel ARM7 core (CoreMP7). The ARM-enabled versions are identified with the
M7 prefix as M7AFS600 and M7AFS1500. The AFS250, AFS600, and AFS1500 devices support the
Actel Cortex-M1 core. The Cortex-M1-enabled versions are identified with the M1 prefix as
M1AFS250, M1AFS600, and M1AFS1500.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-
based Fusion devices are live at power-up and do not need to be loaded from an external boot
PROM. On-board security mechanisms prevent access to the programming information and enable
secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades, with confidence that
valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry-
standard AES algorithm with MAC data authentication on the device. The Fusion family device
architecture mitigates the need for ASIC migration at higher user volumes. This makes the Fusion
family a cost-effective ASIC replacement solution for applications in the consumer, networking and
communications, computing, and avionics markets.
Security
As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable
external bitstream. Fusion devices incorporate FlashLock, which provides a unique combination of
reprogrammability and design security without external overhead, advantages that only an FPGA
with nonvolatile flash programming can offer.
Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure programmed
IP and configuration data. The FlashROM data in Fusion devices can also be encrypted prior to
loading. Additionally, the Flash memory blocks can be programmed during runtime using the
industry-leading AES-128 block cipher encryption standard (FIPS Publication 192). The AES standard
was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the
DES standard, which was adopted in 1977. Fusion devices have a built-in AES decryption engine
and a flash-based AES key that make Fusion devices the most comprehensive programmable logic
device security solution available today. Fusion devices with AES-based security allow for secure
remote field updates over public networks, such as the Internet, and ensure that valuable IP
remains out of the hands of system overbuilders, system cloners, and IP thieves. As an additional
security measure, the FPGA configuration data of a programmed Fusion device cannot be read
back, although secure design verification is possible. During design, the user controls and defines
both internal and external access to the flash memory blocks.
Security, built into the FPGA fabric, is an inherent component of the Fusion family. The Flash cells
are located beneath seven metal layers, and many device design and layout techniques have been
used to make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique
in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected,
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PDF描述 |
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| M1AFS250-FFGG256 | FPGA, 250000 GATES, PBGA256 |
| M1AFS250-FPQ208 | FPGA, 250000 GATES, PQFP208 |
| M1AFS250-FPQG208 | FPGA, 250000 GATES, PQFP208 |
| M1AFS250-FQN180 | FPGA, 250000 GATES, PBCC180 |
| M1AFS250-FQNG180 | FPGA, 250000 GATES, PBCC180 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS250-FFG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFG256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFG256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FFGG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays |
| M1AFS250-FFGG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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