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參數(shù)資料
| 型號： | M1AFS250-FPQ208 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 250000 GATES, PQFP208 |
| 封裝： | 0.50 MM PITCH, PQFP-208 |
| 文件頁數(shù)： | 286/318頁 |
| 文件大小： | 10129K |
| 代理商： | M1AFS250-FPQ208 |
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Actel Fusion Mixed-Signal FPGAs
Pr el iminar y v1 .7
1-3
making secure remote ISP possible. A Fusion device provides the most impenetrable security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
Fusion FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
Flash-based Fusion devices are Level 0 live at power-up (LAPU). LAPU Fusion devices greatly simplify
total system design and reduce total system cost by eliminating the need for CPLDs. The Fusion
LAPU clocking (PLLs) replaces off-chip clocking resources. The Fusion mix of LAPU clocking and
analog resources makes these devices an excellent choice for both system supervisor and system
management functions. LAPU from a single 3.3 V source enables Fusion devices to initiate, control,
and monitor multiple voltage supplies while also providing system clocks. In addition, glitches and
brownouts in system power will not corrupt the Fusion device flash configuration. Unlike SRAM-
based FPGAs, the device will not have to be reloaded when system power is restored. This enables
reduction or complete removal of expensive voltage monitor and brownout detection devices from
the PCB design. Flash-based Fusion devices simplify total system design and reduce cost and design
risk, while increasing system reliability.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
Another source of radiation-induced firm errors is alpha particles. For an alpha to cause a soft or
firm error, its source must be in very close proximity to the affected circuit. The alpha source must
be in the package molding compound or in the die itself. While low-alpha molding compounds are
being used increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.
Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not occur in Fusion Flash-based FPGAs. Once it is
programmed, the flash cell configuration element of Fusion FPGAs cannot be altered by high-
energy neutrons and is therefore immune to errors from them.
Recoverable (or soft) errors occur in the user data SRAMs of all FPGA devices. These can easily be
mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based Fusion devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. With Fusion devices, there is no power-on current
surge and no high current transition, both of which occur on many FPGAs.
Fusion devices also have low dynamic power consumption and support both low power standby
mode and very low power sleep mode, offering further power savings.
Advanced Flash Technology
The Fusion family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows very high logic utilization
(much higher than competing SRAM technologies) without compromising device routability or
performance. Logic functions within the device are interconnected through a four-level routing
hierarchy.
相關PDF資料 |
PDF描述 |
|---|---|
| M1AFS250-FPQG208 | FPGA, 250000 GATES, PQFP208 |
| M1AFS250-FQN180 | FPGA, 250000 GATES, PBCC180 |
| M1AFS250-FQNG180 | FPGA, 250000 GATES, PBCC180 |
| M20-1051700 | 34 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
| M20-1051800 | 36 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP, SOCKET |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1AFS250-FPQ256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FPQ256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FPQ256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M1AFS250-FPQG208 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 208PQFP - Trays |
| M1AFS250-FPQG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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