參數(shù)資料
型號(hào): M25P32
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁(yè)數(shù): 12/48頁(yè)
文件大?。?/td> 386K
代理商: M25P32
Operating features
M25P32
12/48
4.5
Active Power, Standby Power and Deep Power-Down Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
CC2
. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all Write, Program and Erase
instructions (see
Deep Power-down (DP)
) This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
Write, Program or Erase instructions.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions.
4.6.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
4.6.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
4.6.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions.
4.6.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
PP
) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W/V
PP
) signal allow the device to be put in the Hardware Protected mode. In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
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