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參數(shù)資料
| 型號(hào)： | M25P40-VMN6P |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 32/40頁 |
| 文件大小： | 232K |
| 代理商： | M25P40-VMN6P |
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M25P40
32/40
Table 17. AC Characteristics (25MHz Operation, Device Grade 6 or 3)
Note: 1. t
CH
+ t
CL
must be greater than or equal to 1/ f
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. For device grade 3, this is Preliminary Data
Test conditions specified in
Table 9.
and
Table 16.
Symbol
Alt.
Parameter
Min.
5
Typ.
Max.
5
Unit
f
C
f
C
Clock Frequency for the following instructions:
FAST_READ, PP SE, BE, DP RES,
WREN, WRDI, RDSR, WRSR
D.C.
25
MHz
f
R
Clock Frequency for READ instructions
D.C.
20
MHz
t
CH 1
t
CLH
Clock High Time
18
ns
t
CL 1
t
CLL
Clock Low Time
18
ns
t
CLCH 2
Clock Rise Time
3
(peak to peak)
0.1
V/ns
t
CHCL 2
Clock Fall Time
3
(peak to peak)
0.1
V/ns
t
SLCH
t
CSS
S Active Setup Time (relative to C)
10
ns
t
CHSL
S Not Active Hold Time (relative to C)
10
ns
t
DVCH
t
DSU
Data In Setup Time
5
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
CHSH
S Active Hold Time (relative to C)
10
ns
t
SHCH
S Not Active Setup Time (relative to C)
10
ns
t
SHSL
t
CSH
S Deselect Time
100
ns
t
SHQZ 2
t
DIS
Output Disable Time
15
ns
t
CLQV
t
V
Clock Low to Output Valid
15
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
HLCH
HOLD Setup Time (relative to C)
10
ns
t
CHHH
HOLD Hold Time (relative to C)
10
ns
t
HHCH
HOLD Setup Time (relative to C)
10
ns
t
CHHL
HOLD Hold Time (relative to C)
10
ns
t
HHQX 2
t
LZ
HOLD to Output Low-Z
15
ns
t
HLQZ 2
t
HZ
HOLD to Output High-Z
20
ns
t
WHSL 4
Write Protect Setup Time
20
ns
t
SHWL 4
Write Protect Hold Time
100
ns
t
DP 2
S High to Deep Power-down Mode
3
μ
s
t
RES1 2
S High to Standby Mode without Electronic
Signature Read
3
μ
s
t
RES2 2
S High to Standby Mode with Electronic
Signature Read
1.8
μ
s
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