參數(shù)資料
型號(hào): M25P64-VMF6T
廠商: 意法半導(dǎo)體
英文描述: 16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
中文描述: 64兆位,低電壓,串行閃存與50MHz的SPI總線接口內(nèi)存
文件頁(yè)數(shù): 11/38頁(yè)
文件大?。?/td> 519K
代理商: M25P64-VMF6T
11/38
M25P64
MEMORY ORGANIZATION
The memory is organized as:
8388608 bytes (8 bits each)
128 sectors (512Kbits, 65536 bytes each)
32768 pages (256 bytes each).
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
Figure 8. Block Diagram
AI08520
HOLD
S
W
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
7FFFFFh
000FFh
相關(guān)PDF資料
PDF描述
M25P64-VMF6P 4 Mbit Uniform Sector, Serial Flash Memory
M25P64-VMF6TG 4 Mbit Uniform Sector, Serial Flash Memory
M25P64-VMF6TP 4 Mbit Uniform Sector, Serial Flash Memory
M25PE80-VMP6G 4 Mbit Uniform Sector, Serial Flash Memory
M25PE80-VMP6P 4 Mbit Uniform Sector, Serial Flash Memory
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