參數(shù)資料
型號: M25P64-VMF6T
廠商: 意法半導(dǎo)體
英文描述: 16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
中文描述: 64兆位,低電壓,串行閃存與50MHz的SPI總線接口內(nèi)存
文件頁數(shù): 20/38頁
文件大小: 519K
代理商: M25P64-VMF6T
M25P64
20/38
Read Data Bytes (READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency f
R
, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in
Figure 14.
.
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
Figure 14. Read Data Bytes (READ)
Instruction Sequence and Data-Out Sequence
Note: 1. Address bit A23 is Don’t Care.
C
D
AI03748D
S
Q
23
2
1
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35
22 21
3
2
1
0
36 37 38
7
6
5
4
3
1
7
0
High Impedance
Data Out 1
Instruction
24-Bit Address
0
MSB
MSB
2
39
Data Out 2
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