參數(shù)資料
型號: M25P64-VMF6T
廠商: 意法半導體
英文描述: 16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
中文描述: 64兆位,低電壓,串行閃存與50MHz的SPI總線接口內(nèi)存
文件頁數(shù): 15/38頁
文件大小: 519K
代理商: M25P64-VMF6T
15/38
M25P64
Write Enable (WREN)
The Write Enable (WREN) instruction (
Figure 9.
)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (
Figure 10.
)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction
completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 10. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
相關PDF資料
PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
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