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參數(shù)資料
| 型號： | M25PE80-VMP6TP |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 14/43頁 |
| 文件大小： | 599K |
| 代理商： | M25PE80-VMP6TP |
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M25PE80
14/43
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-Byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Table 6.
Every instruction sequence starts with a one-Byte
instruction code. Depending on the instruction,
this might be followed by address Bytes, or by data
Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Identification (RDID), Read Status Register (RD-
SR), or Read Lock Register (RDLR) instruction,
the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is be-
ing shifted out.
In the case of a Page Write (PW), Page Program
(PP), Write to Lock Register (WRLR), Page Erase
(PE), Sector Erase (SE), Bulk Erase (BE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven High exactly at a Byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ig-
nored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
Table 6. Instruction Set
Instruction
Description
One-Byte Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDID
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to
∞
WRLR
Write to Lock Register
1110 0101
E5h
3
0
1
RDLR
Read Lock Register
1110 1000
E8h
3
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to
∞
FAST_READ Read Data Bytes at Higher Speed
0000 1011
0Bh
3
1
1 to
∞
PW
Page Write
0000 1010
0Ah
3
0
1 to 256
PP
Page Program
0000 0010
02h
3
0
1 to 256
PE
Page Erase
1101 1011
DBh
3
0
0
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
DP
Deep Power-down
1011 1001
B9h
0
0
0
RDP
Release from Deep Power-down
1010 1011
ABh
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE80 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMP6 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMW6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMW6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE80-VMW6T | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE80-VMS6G | 制造商:Micron Technology Inc 功能描述:NOR Flash Serial-SPI 3.3V 8Mbit 1M x 8bit 8ns 8-Pin QFN Tray |
| M25PE80-VMS6P | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE80-VMS6TG | 功能描述:IC FLASH 8MBIT 75MHZ 8QFN RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Forté™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| M25PE80-VMS6TP | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE80-VMW6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit, Low Voltage, Page-Erasable Serial Flash Memory with Byte-Alterability, 50MHz SPI Bus, Standard Pin-out |
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